102A01001

記憶體

型號：XC1736DPC

• 1.設定一次性可程式 (OTP) 唯讀記憶體，用於儲存 Xilinx FPGA 裝置的設定位元流 Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices

• 2.片上位址計數器，時脈輸入的每個上升沿遞增 On-chip address counter, incremented by each rising edge on the clock input

• 3.簡單的 FPGA 介面只需要一個使用者/O 接腳 Simple interface to the FPGA requires only one user/O pin

• 4.可級聯儲存更長或多個位元流 Cascadable for storing longer or multiple bitstreams

• 5.可程式重設極性（高電平有效或低電平有效），相容於不同的 FPGA 解決方案 Programmable reset polarity(active High or activeLow) for compatibility with diferent FPGA solutions

• 6.低功耗 CMOS EPROM 製程· 僅提供 5V 版本 Low-power CMOS EPROM process· Available in 5V version only

• 7.由領先的程式設計器製造商提供程式支援。 Programming support by leading programmer manufacturers.

• 8.使用 Xilinx Alliance 和 Foundation 系列軟體包進行設計支援。 Design support using the Xilinx Alliance and Foundation series software packages.

• 9.安裝類型：通孔式

• 10.封裝：DIP-8

XC1700D QPRO™ 系列配置 PROM 提供了一種易於使用、經濟高效的方法來儲存 Xilinx FPGA 配置位元流。當 FPGA 處於主串列模式時，它會產生驅動 PROM 的配置時脈。時脈上升沿後的短暫存取時間內，資料出現在連接到 FPGA DIN 接腳的 PROM DATA 輸出接腳上。 FPGA 產生適當數量的時脈來完成配置。一旦配置完成，它將停用 PROM。當 FPGA 處於從屬串列模式時，PROM 和 FPGA 都必須由輸入訊號進行時脈控制。可以透過使用 CEO 輸出驅動後續設備的 CE 輸入來連接多個設備。此鏈中所有 PROM 的時脈輸入和資料輸出都是互連的。所有設備均相容並可與家庭其他成員級聯。對於設備編程，Xilinx Alliance™ 或 Foundation™ 系列開發系統將 FPGA 設計文件編譯為標準 HEX 格式，然後將其傳輸到大多數商業 PROM 編程器。 The XC1700D QPRO™ family of configuration PROMs provide an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance™ or the Foundation™ series development systems compiles the FPGA design file into a standard HEX format which is then transferred to most commercial PROM programmers.